The present invention relates generally to semiconductor memory devices, and more particularly to the arrangement of memory cell arrays within a semiconductor memory device.
The fabrication of semiconductor devices typically includes the depositing and patterning of fabrication layers. In general, the fabrication of a device can start with the patterning of a semiconductor substrate into active area portions separated from one another by insulation. Subsequent alternating insulation and conductive layers are then formed over, and sometimes coupled to the substrate, to create and interconnect various circuit elements (such as transistors, capacitors and the like).
The patterning of an insulation or conductive layer usually involves a lithography and etch step. The lithography step involves depositing an alterable material, referred to as a xe2x80x9cresistxe2x80x9d on the layer that is to be patterned. The resist is then xe2x80x9cdevelopedxe2x80x9d or xe2x80x9cprintedxe2x80x9d into a pattern by the application of some form of radiation. For example, xe2x80x9cphotoresistsxe2x80x9d can be patterned by the application of light. Other resists can be patterned by x-rays, electron beams or ion beams, to name just a few examples. The pattern within a resist is typically developed by situating a xe2x80x9cmaskxe2x80x9d containing the desired pattern over the resist. The mask includes xe2x80x9ctransparentxe2x80x9d portions that will allow radiation to pass through, and xe2x80x9cblockingxe2x80x9d portions that will block the radiation. When the radiation is applied, the areas of resist situated below the transparent mask portions will be developed, those below blocking portions will not be developed. The undeveloped portions of resist can then be removed with a solvent, leaving the desired pattern over the fabrication layer.
The developed pattern of resist can then serve as an etch mask for the fabrication layer below. An etch can is applied, and those portions of the fabrication layer that are covered by the etch mask will be protected from the etch. The exposed portions will be removed. In this manner structures or xe2x80x9cfeaturesxe2x80x9d are formed in the fabrication layer by the etch step. For example, in the event the fabrication layer is a conductive layer, the etch step can create conductive interconnects between various portions of a device. In the event the fabrication layer is an insulation layer, the etch step can create contact holes through the insulation layer to a conductive layer below.
In order to fabricate as small a semiconductor device as possible, and hence produce such devices in a more cost effective manner, efforts are continually made to form features with as small a size as possible. The smallest manufacturable feature size is often referred to as a minimum feature size. The minimum feature size will determine how close structures can be situated relative to one another in the semiconductor device.
In addition to impacting the resulting size of a semiconductor device, feature sizes can also play an important part in the functionality of a semiconductor device. For example, in order to create accurate etch mask patterns from a layer of resist, sufficient radiation must be applied to the resist to print the pattern. However, as masks are made for devices having increasingly smaller features sizes, it becomes more and more difficult to control the resulting radiation intensity necessary to produce uniform feature sizes across a semiconductor device.
One particular type of semiconductor device in which minimum feature sizes can play an important role is the semiconductor memory device. Semiconductor memory devices typically include an array of densely packed memory cells, surrounded by a periphery of ancillary circuits. An example of a semiconductor memory device is set forth in a top plan view in FIG. 1, The memory device is designated by the general reference character 100 and shown to include a memory cell array 102 surrounded by a periphery region 104. The memory cell array 102 can include thousands of memory cells accessed by word lines and bit lines (not shown in FIG. 1). FIG. 1 further includes a number of dots, one of which is shown as item 106. Each of the dots represents the location of failed memory cells. As shown in the figure, the failed memory cells 106 are prevalent on the peripheral (edge) portions of the memory cell array 102.
The prevalence of failed memory cells on the peripheral portions of the array is further understood by referring to FIG. 2. FIG. 2 sets forth a corner portion of the memory cell array 102, shown as item 108 in FIG. 1. The array portion of FIG. 2 is identified by the general reference character 200, and illustrates word lines 202 and bit lines 204. The bit lines 204 are separated from one another by a uniform distance (shown as d1). Similarly, the word lines 202 are separated from one another by a uniform distance (shown as d2). The right-most bit line can be considered to define a right edge of the array, and the bottom-most word line can be considered to define a bottom edge of the array. Typically, the word lines 202 and bit lines 204 are formed with minimum feature sizes, and minimum distances between adjacent lines (pitch). Consequently, the memory cell array has a much higher feature density than the surrounding peripheral portions of the semiconductor memory device.
A problem associated with situating dense features (such as a memory cell array) adjacent to less dense features (such as those found in the periphery of a memory device) is that of proximity effects. Proximity effects result in non-uniform transferring of a pattern from a mask to the resist layer below. Such effects can arise in photolithography due to the diffraction of light caused by the difference in feature densities. Proximity effects are also known to incur in other types of lithography systems, such as those utilizing electron beam lithography. Thus, while a given mask pattern will produce a given feature in the central portion of the array, using the same mask in the periphery array can result in different feature sizes, and hence defects on the edge of the array.
One approach for addressing the adverse results of proximity effects is to include sacrificial (xe2x80x9cdummyxe2x80x9d) memory cells on the periphery of the array. Referring once again to FIG. 2, the portion of the array 200 is shown to include dummy rows of memory cells 206 and dummy columns of memory cells 208. The dummy memory cells are not functional and serve to xe2x80x9cabsorbxe2x80x9d the proximity effect caused by the junction of the memory cell array and the periphery.
As the feature sizes of semiconductor devices continues to shrink, proximity effects will require more and more dummy memory cells. Such use of increased numbers of dummy memory cells can waste valuable area in the memory device.
It would be desirable to arrive at some way to address proximity effects without having to increase the number of sacrificial devices, such as dummy memory cells as is the case in semiconductor memory devices.
According to the preferred embodiment, a semiconductor memory device includes an array of memory cells arranged into rows and columns. The memory cells of like columns are commonly coupled to a bit line, the memory cells of like rows are commonly coupled to a word line. While the majority of the bit lines and word lines within the memory cell array have the same spacing (pitch), the word lines and bit lines on the periphery of the array have an increased pitch. As a result, the proximity effects on the edge of the memory cell array can be reduced, and fewer dummy memory cells are required.
According to one aspect of the preferred embodiment, the increase in pitch of bit lines and word lines on the periphery of the array is 5%-10% greater than that of the other word lines and bit lines of the array.
According to another aspect of the preferred embodiment, the semiconductor memory device is a dynamic random access memory having one transistor-one capacitor memory cells.